From Graphite Pencil to Global Impact
For over a century, IBM researchers transformed mathematical pencil schematics into the foundational physical hardware of modern civilization. Explore the top 1,000 high-value patents—complete with original draftsman patent figures, plain-English breakthroughs, and the legendary commercial products they created.
Draftsman Sketch vs. First Commercial Product
Drag the center slider to inspect how the patent drawing translated into the commercial product.
IBM SQL/DS & IBM DB2
Market Launch: 1981
The foundational database software powering global banking, commerce, and enterprise computing.
SQL remains the world's most widely adopted data language, powering Oracle, PostgreSQL, MySQL, and Microsoft SQL Server.
Relational Database Model & SQL
Inventor: Edgar F. Codd (1978)
"Codd invented the relational algebra model, separating logical data relationships into tables of rows and columns. Chamberlin and Boyce created Structured English Query Language (SEQUEL/SQL), allowing users to declare WHAT data they wanted, not HOW to retrieve it."
System and Method for Parsing and Evaluating Relational Queries
The Problem: Early enterprise databases stored records in complex hierarchical tree structures. Programmers had to write complex procedural code knowing the exact physical storage path to find any customer or transaction.
The Patent Catalog
Displaying 24 of 1000 filtered patents
Relational Database Model & SQL
Codd invented the relational algebra model, separating logical data relationships into tables of rows and columns. Chamberlin and Boyce created Structured English Query Language (SEQUEL/SQL), allowing users to declare WHAT data they wanted, not HOW to retrieve it.
Fault-Tolerant Surface Code Decoder
Introduces fault-tolerant surface code decoder with graph-based minimum-weight perfect matching incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Graph Neural Network Embedding Architecture
Introduces graph neural network embedding architecture for molecular property prediction incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Adaptive Noise-Canceling Dual-Microphone Array
Introduces adaptive noise-canceling dual-microphone array with spatial beamforming incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
1-Transistor DRAM Memory Cell
Dennard realized that a single field-effect transistor paired with a microscopic electrical capacitor could store a binary '1' or '0' as a tiny electrical charge. This slashed memory cost by orders of magnitude and paved the way for modern microcomputing.
Plasmonic Surface Resonator
Introduces plasmonic surface resonator for sub-micron optical interconnects incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Adaptive Write-Back Cache Controller
Introduces adaptive write-back cache controller with dynamic prefetch throttling incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Superscalar Execution Unit
Introduces superscalar execution unit with dynamic speculative branch prediction incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Touch-Sensitive Transparent Display Overlay
Introduces touch-sensitive transparent display overlay with multiplexed capacitive electrodes incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Analog In-Memory Matrix-Vector Multiplier Using Non-Volatile Phase Change Arrays
Introduces analog in-memory matrix-vector multiplier using non-volatile phase change arrays incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
RISC Processor Architecture
John Cocke demonstrated that 80% of computation relied on 20% of simple instructions. By designing a streamlined processor that executed one simple instruction per single clock cycle with a deep pipeline and optimizing compiler, speed jumped dramatically.
Point-of-Sale Contactless Near-Field Communication (NFC) Secure Cryptoprocessor
Introduces point-of-sale contactless near-field communication (nfc) secure cryptoprocessor incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Point-of-Sale Contactless Near-Field Communication (NFC) Secure Cryptoprocessor
Introduces point-of-sale contactless near-field communication (nfc) secure cryptoprocessor incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Superscalar Execution Unit
Introduces superscalar execution unit with dynamic speculative branch prediction incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Atomic Precision Scanning Probe Lithography
Introduces atomic precision scanning probe lithography with hydrogen depassivation incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Automated Vectorized Query Execution Engine
Introduces automated vectorized query execution engine for relational analytical processing incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Smart Card Dual-Interface Chip
Introduces smart card dual-interface chip with shared cryptographic engine incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Deep Learning Attention Cache Compression via Dynamic Quantization and Eviction
Introduces deep learning attention cache compression via dynamic quantization and eviction incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Scanning Tunneling Microscope (STM)
Binnig and Rohrer at IBM Zurich Research Laboratory utilized quantum mechanical electron tunneling: bringing an atom-sharp tungsten tip within nanometers of a surface so electrons tunnel across the vacuum gap, measuring surface topography atom by atom.
Electrostatically Driven Inkjet Nozzle Array
Introduces electrostatically driven inkjet nozzle array with drop-on-demand modulation incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Non-Volatile Magnetoresistive RAM (MRAM) Spin-Torque Transfer Cell
Introduces non-volatile magnetoresistive ram (mram) spin-torque transfer cell incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Graph Neural Network Embedding Architecture
Introduces graph neural network embedding architecture for molecular property prediction incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
Trans
Introduces transformer self-attention matrix multiplication accelerator with sparse sparsity incorporating synchronous pipelining and hardware feedback loops, drastically reducing latency while increasing reliability.
The IBM Personal Computer (PC 5150)
Estridge's 'Project Chess' team in Boca Raton, Florida broke IBM tradition by creating an open architecture machine using commercial off-the-shelf parts (Intel 8088 CPU, Microsoft DOS) with Mark Dean's 16-bit ISA expansion bus.